Intel Agilex Series

3.2.2. AS Single-Device Configuration
Figure 38. Connections for AS x4 Single-Device Configuration
Pin 1
R
UP
R
DN
R
UP
TCK
TDO
TMS
OPEN
TDI
GND
VCCIO_SDM
OPEN
OPEN
GND
G
ND
V
CCIO_SDM
Intel FPGA
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
AS_DATA[3:0]
AS x4 Flash Memory
AS_CLK
AS_nCSO[0]
Download cable 10 pin male header
DATA[3:0]
DCLK
nCS
Configuration
Control Signals
Optional
Monitoring
10kΩ
Optional
Configuration
Data Signals
To JTAG
Header or
JTAG Chain
MSEL
V
CCIO_SDM
3
4
TCK
TDO
TDI
TMS
JTAG
Configuration
Pins
FPGA
Image (.rpd)
10kΩ
AS_nRST
nReset
Resistor values can vary between 1 kΩ to 10 kΩ.
Perform signal integrity analysis to select
the resistor value for your setup.
Related Information
MSEL Settings on page 29
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
Intel
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Agilex
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Configuration User Guide
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