Intel Agilex Series

3.2.1. AS Configuration Scheme Hardware Components and File Types ......................................................................... 103
3.2.2. AS Single-Device Configuration....................................................................................................................... 106
3.2.3. AS Using Multiple Serial Flash Devices..............................................................................................................107
3.2.4. AS Configuration Timing Parameters................................................................................................................ 108
3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines....................................................................... 109
3.2.6. Programming Serial Flash Devices................................................................................................................... 110
3.2.7. Serial Flash Memory Layout............................................................................................................................114
3.2.8. AS_CLK....................................................................................................................................................... 115
3.2.9. Active Serial Configuration Software Settings ................................................................................................... 116
3.2.10. Intel Quartus Prime Programming Steps......................................................................................................... 117
3.2.11. Debugging Guidelines for the AS Configuration Scheme.................................................................................... 123
3.3. JTAG Configuration....................................................................................................................................................124
3.3.1. JTAG Configuration Scheme Hardware Components and File Types....................................................................... 126
3.3.2. JTAG Device Configuration..............................................................................................................................127
3.3.3. JTAG Multi-Device Configuration......................................................................................................................130
3.3.4. Debugging Guidelines for the JTAG Configuration Scheme...................................................................................132
4. Including the Reset Release Intel FPGA IP in Your Design................................................................................................. 134
4.1. Understanding the Reset Release IP Requirement.......................................................................................................... 135
4.2. Instantiating the Reset Release IP In Your Design..........................................................................................................137
4.3. Gating the PLL Reset Signal........................................................................................................................................137
4.4. Guidance When Using Partial Reconfiguration (PR).........................................................................................................138
4.5. Detailed Description of Device Configuration................................................................................................................. 138
4.5.1. Device Initialization....................................................................................................................................... 140
4.5.2. Preventing Register Initialization During Power-On ............................................................................................140
4.5.3. Embedded Memory Block Initial Conditions....................................................................................................... 142
4.5.4. Protecting State Machine Logic........................................................................................................................142
5. Remote System Update (RSU)............................................................................................................................................ 144
5.1. Remote System Update Functional Description.............................................................................................................. 146
5.1.1. RSU Glossary................................................................................................................................................146
5.1.2. Remote System Update Using AS Configuration.................................................................................................148
5.1.3. Remote System Update Configuration Images ..................................................................................................149
5.1.4. Remote System Update Configuration Sequence................................................................................................150
5.1.5. RSU Recovery from Corrupted Images............................................................................................................. 151
5.1.6. Updates with the Factory Update Image........................................................................................................... 154
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Intel
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Agilex
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Configuration User Guide
3