Intel Agilex Series

3.3.2.1. JTAG Single-Device Configuration using Download Cable Connections
Figure 51. Connection Setup for JTAG Single-Device Configuration using Download Cable
Intel FPGA
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
TCK
TDO
TDI
TMS
Configuration
Control Signals
JTAG
Configuration
Pins
Optional
Monitoring
To JTAG
Header or
JTAG Chain
10kΩ
MSEL
V
CCIO_SDM
3
Pin 1
Download cable 10 pin male header (JTAG mode)
R
UP
R
DN
R
UP
TCK
TDO
TMS
OPEN
TDI
GND
VCCIO_SDM
OPEN
OPEN
GND
G
ND
V
CCIO_SDM
10k
Ω
Resistor values can vary between 1 kΩ to 10 kΩ.
Perform signal integrity analysis to select
the resistor value for your setup.
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
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