After nINIT_DONE asserts (low), all logic is in user mode and operates normally. You can use the nINIT_DONE signal in one
of the following ways:
• To gate an external or internal reset.
• To gate the reset input to the transceiver and I/O PLLs.
• To gate the write enable of design blocks such as embedded memory blocks, state machine, and shift registers.
• To synchronously drive register reset input ports in your design.
Attention:
If you use multiple Reset Release Intel FPGA IP instances in your design, the nINIT_DONE signals are driven directly from the
same source in SDM.
4. Including the Reset Release Intel FPGA IP in Your Design
683673 | 2021.10.29
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