Register B in the active section is operational and takes on the value of Register A in the next clock cycle. Register A is still in
the freeze register state and does not respond to the clock edge. Register A remains in the current state.
Figure 60. Advance One Clock Cycle, Device Completely In User Mode - INIT_DONE = 1
1
O
Register A
Register B
Register C
Error
1
Functional (Row N)
Functional (Row N+1)
The entire fabric is now in user mode. The state machine enters an illegal or unknown state with two ones in a one-hot state
machine. To prevent this illegal state, use the Reset Release IP to hold the circuit in reset until INIT_DONE asserts indicating
that the entire fabric has entered user mode.
4. Including the Reset Release Intel FPGA IP in Your Design
683673 | 2021.10.29
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Configuration User Guide
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