Intel Agilex Series

Command Code
(Hex)
Command
Length
(14)
Response
Length
(14)
Description
• The opcode for the write command.
• The number of bytes to write.
• The data to write.
To perform a sector erase or sub-sector erase, you must specify the serial flash address in most
significant byte (MSB) to least significant byte (LSB) order as the following example illustrates.
To erase a sector of a Micron 2 gigabit (Gb) flash at address 0x04FF0000 using the
QSPI_WRITE_DEVICE_REG command, write the flash address in MSB to LSB order as shown
here:
Header: 0x00003036
Opcode: 0x000000DC
Number of bytes to write: 0x00000004
Flash address: 0x0000FF04
A successful write returns the OK response code. This command pads data that is not a multiple
of 4 bytes to the next word boundary. The command pads the data with zero.
Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad
SPI Flash on page 158.
QSPI_SEND_
DEVICE_OP
37 1 0 Sends a command opcode to the quad SPI. Takes one argument:
• The opcode to send the quad SPI device.
A successful command returns the OK response code.
Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad
SPI Flash on page 158.
For CONFIG_STATUS and RSU_STATUS major and minor error code descriptions, refer to Appendix: CONFIG_STATUS and
RSU_STATUS Error Code Descriptions in the Mailbox Client Intel FPGA IP User Guide.
Related Information
•
Mailbox Client Intel FPGA IP User Guide: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
For more information about the CONFIG_STATUS and RSU_STATUS error codes.
• Intel Agilex Hard Processor System Remote System Update User Guide
(14)
This number does not include the command or response header.
5. Remote System Update (RSU)
683673 | 2021.10.29
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Configuration User Guide
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