Intel Agilex Series

The SDM drives Intel Agilex device configuration.
Power-On Status
The power-on reset (POR) holds the Intel Agilex device in the reset state until the power supply outputs are within the
recommended operating range. t
RAMP
defines the maximum power supply ramp time. If power supplies ramp time do not
meet the t
RAMP
time, the Intel Agilex device I/O pins state is unknown.
For more information about POR refer to the Intel Agilex Power Management User Guide. For more information about t
RAMP
refer to the Intel Agilex Device Datasheet.
Initial Configuration Timing
The first section of the figure shows the expected timing for initial configuration after a normal power-on reset . Initially, the
application logic drives the nCONFIG signal low (POR). Under normal conditions nSTATUS follows nCONFIG because nSTATUS
reflects the current configuration state. nCONFIG must only change when it has the same value as nSTATUS.
Note:
To receive a valid nSTATUS response from the device, your host must only monitor this signal after the device power group 3
is powered up to the recommended operating condition and after the maximum POR delay specification is met. For more
information, refer to the POR delay specification in Intel Agilex Device Data Sheet.
When an error occurs, nSTATUS pulses low and asserts high when the device is ready to accept reconfiguration.
The numbers in the Initial Configuration part of the timing diagram mark the following events:
1.
The SDM boots up and samples the MSEL signals to determine the specified FPGA configuration scheme. The SDM does
not sample the MSEL pins again until the next power cycle.
2.
With the nCONFIG signal low, the SDM enters Idle mode after booting.
2. Intel Agilex Configuration Details
683673 | 2021.10.29
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Configuration User Guide
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