Intel Agilex Series User Manual

Figure 89. Intel Agilex CvP Configuration Block Diagram
Intel FPGA
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
AS_DATA[3:0]
AS_CLK
AS_nCSO[0]
Configuration
Control Signals
Configuration
Control Signals
Optional
Monitoring
10kΩ
MSEL
V
CCIO_SDM
AS x4 Flash Memory
DATA[3:0]
DCLK
nCS0
PCIe Link
Core Image
Update via
PCIe Link
3
4
Periphery
Image (.jic)
PCIe Host
Core Image
(.rbf)
1
2
3
n
End
Point
Core Image
PCIe
Hard IP
(HIP)
Secure
Device
Manager
FPGA Fabric
Root
Complex
CVP_CONFDONE (optional)
10kΩ
6. Intel Agilex Configuration Features
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Intel Agilex Series Specifications

General

Architecture	FPGA
AI Tensor Blocks	Yes
Category	FPGA
Family	Agilex
Transceiver Speed	Up to 112 Gbps
Manufacturer	Intel
Series	Agilex
Transceiver Data Rate	Up to 112 Gbps
Memory Support	HBM2E
PCIe Support	PCIe 5.0
Memory	HBM2e
Power Efficiency	Improved over previous generations
Operating Temperature	Commercial, Industrial
Process Technology	10nm