Intel Agilex Series

Document Version Intel Quartus
Prime Version
Changes
• Removed the following sections from the Avalon-ST Configuration scheme:
— QSF Assignment for Avalon-ST x8
— QSF Assignment for Avalon-ST x16
— QSF Assignment for Avalon-ST x32
• Added the following restriction in the Avalon ST Configuration section: Access to the I/O pins located in bank 3A with pin
index[91...95] is not allowed for the AVSTx16 or x32 configuration scheme. You must leave these pins unconnected. For
more information, refer to the device pin mapping files to identify the exact pin location.
• Updated AS Configuration section:
— Revised Required Configuration Signals for the AS Configuration Scheme table. Removed outdated table description.
—
Revised AS_nCSO statement in the MSEL Pin Function for the AS x4 Configuration Scheme section.
—
Corrected OSC_CLK_1 frequency from 80 MHz to 71.5 MHz in the Maximum AS_CLK Frequency as a Function of Board
Capacitance Loading and Clock Source and the Supported Configuration Clock Source and AS_CLK Frequencies in Intel
Agilex Devices table.
—
Added new table: T
ext_delay
as a Function of AS_CLK Frequency in the AS Configuration Timing Parameters section.
—
Added notes in the Supported configuration clock source and AS_CLK Frequencies in Intel Agilex Devices table
clarifying that you observe a lower AS_CLK frequency when accessing the flash during user mode.
— Revised step describing the programming file(s) generation in the Generating Programming Files using the
Programming File Generator. Added command to save the programming file.
• Removed guidelines related to SD/MMC device configuration in the following sections:
— Removed SD/MMC flash memories support in the Intel Agilex Configuration Overview section.
— Removed SD/MMC configuration scheme from the Intel Agilex Configuration Data Width, Clock Rates, and Data Rates
table.
— Removed SD/MMC interface from the Intel Agilex Configuration Interfaces figure.
— Removed SD/MMC block from the SDM Block Diagram figure and the corresponding description.
— Removed SD/MMC x4/x8 configuration scheme from the MSEL Settings for Each Configuration Scheme of Intel Agilex
Devices table.
—
Removed SD/MMC text from the CLIENT_ID_NO_MATCH description in the Error Codes table.
•
Updated the JTAG Configuration section to include .rbf file as supported option to configure FPGA using the Intel Quartus
Prime Programmer.
•
Updated recommendations on how to debug the OSC_CLK_1 clock based configuration in the Debugging Guidelines for the
AS Configuration Scheme topic.
•
Removed UNKNOWN_BR error from the Error Codes table.
• Removed PUF data from flash memory section and figures. For more information, refer to the Intel Stratix 10 Device
Security User Guide.
• Revised step on selecting factory and application images in the Generating the Initial RSU Image and the Creating Initial
Flash Image Containing Bitstreams for Factory Image and One Application Image sections.
• Revised flash offset for factory image, sub-partition tables, pointer blocks, and application images in the Flash Sub-
Partitions Layout table.
continued...
9. Document Revision History for the Intel Agilex Configuration User Guide
683673 | 2021.10.29
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