Intel Agilex Series

Document Version Intel Quartus
Prime Version
Changes
•
Added the following restriction to the definition of QSPI_SET_CS: Access to the QSPI flash memory devices using SDM_IO
pins is only available for the AS x4 configuration scheme, JTAG configuration, and a design compiled for ASx4
configuration. For the Avalon ST configuration scheme, you must connect QSPI flash memories to GPIO pins.
• Removed support for a 16-byte Version ID as the first 16 bytes of the application image. This feature is not supported in
Intel Agilex devices.
• Updated the final suggestion in Debugging Guidelines for the JTAG Configuration Scheme topic, to the following: When the
MSEL setting on the PCB is not JTAG, if you use the JTAG interface for reconfiguration after an initial reconfiguration using
AS or the Avalon-ST interface, the .sof must be in the file format you specified in the Intel Quartus Prime project. For
example, if you initially configure the MSEL pins for AS configuration and configure using the AS scheme, a subsequent
JTAG reconfiguration using a .sof generated for Avalon-ST fails.
2019.10.09 19.3 Made the following changes:
•
Corrected definition of RSU_STATUS command. This command has 9, not 10 words.
• Added E-Tile Transceivers May Fail To Configure to the Debugging chapter.
• Revised the Modifying the List of Application Images topic.
2019.09.30 19.3 Made the following changes to the device and software:
•
Added the optional nCATTRIP (catastrophic trip) SDM I/O signal. This signal asserts when the core temperature is greater
than 125° C.
•
Added the an eighth word to the to the RSU_STATUS response: Word 8: Current image retry counter.
•
Added new field to the 5th word of the RSU_STATUS response. This field specifies the source of a reported error.
•
Added RSU_NOTIFY to the available operation commands.
• Changed the number of images that the Programming File Generator supports from 3 to 7.
• Removed write restrictions for lower addresses in flash memory. (The device firmware must still reside at address 0x0.)
Made the following changes to the user guide:
• Added many topics showing how to implement in the Intel Quartus Prime Pro Edition Software.
• Changed the err status pulse range from 1 ms ±50% to 0.5 ms to 10 ms.
• Removed the SDM Firmware state from the Intel Intel Agilex FPGA Configuration Flow diagram. This state is part of the
FPGA Configuration state.
• Updated recommendations on how to debug a corrupt configuration bitstream for the AS x4 configuration scheme in the
Debugging Guidelines for the AS Configuration Scheme topic.
•
Corrected the signal name in The AVST_READY Signal topic: The device can starting sending data when AVST_READY
asserts.
• Added note that the Avalon ST x32 configuration scheme is limited to 3, DDR x72 DDR external memory interfaces. The
Avalon ST x8 and x16 configuration schemes can support up to 4, x72 DDR external memory interfaces.
• Corrected the Pin Type in the Required Configuration Signals for the Avalon-ST Configuration Scheme table.
AVSTx8_READY is an SDM I/O pin. AVST_READY is a GPIO or Dual-Purpose pin.
• Corrected minor errors and typos.
continued...
9. Document Revision History for the Intel Agilex Configuration User Guide
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
Send Feedback
228