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INVT Goodrive350 IP55

INVT Goodrive350 IP55
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Goodrive350 IP55 High-ingress Protection Series VFD Basic Operation Instructions
-100-
Function
code
Name
Description
Default
value
P10.12
Multi-step speed 5
-300.0300.0%
0.0%
P10.13
Running time of 5
th
step
0.06553.5s (min)
0.0s
P10.14
Multi-step speed 6
-300.0300.0%
0.0%
P10.15
Running time of 6
th
step
0.06553.5s (min)
0.0s
P10.16
Multi-step speed 7
-300.0300.0%
0.0%
P10.17
Running time of 7
th
step
0.06553.5s (min)
0.0s
P10.18
Multi-step speed 8
-300.0300.0%
0.0%
P10.19
Running time of 8
th
step
0.06553.5s (min)
0.0s
P10.20
Multi-step speed 9
-300.0300.0%
0.0%
P10.21
Running time of 9
th
step
0.06553.5s (min)
0.0s
P10.22
Multi-step speed 10
-300.0300.0%
0.0%
P10.23
Running time of 10
th
step
0.06553.5s (min)
0.0s
P10.24
Multi-step speed 11
-300.0300.0%
0.0%
P10.25
Running time of 11
th
step
0.06553.5s (min)
0.0s
P10.26
Multi-step speed 12
-300.0300.0%
0.0%
P10.27
Running time of 12
th
step
0.06553.5s (min)
0.0s
P10.28
Multi-step speed 13
-300.0300.0%
0.0%
P10.29
Running time of 13
th
step
0.06553.5s (min)
0.0s
P10.30
Multi-step speed 14
-300.0300.0%
0.0%
P10.31
Running time of 14
th
step
0.06553.5s (min)
0.0s
P10.32
Multi-step speed 15
-300.0300.0%
0.0%
P10.33
Running time of 15
th
step
0.06553.5s (min)
0.0s
P10.34
Acceleration/deceleration
time selection of 07
section of simple PLC
0x00000XFFFF
0x0000
P10.35
Acceleration/ deceleration
time selection of 815
section of simple PLC
0x00000XFFFF
0x0000
P17.27
Acutal stage of simple PLC
Displays the present stage of the simple
PLC function.
0
5.5.15 PID control
PID control, a common mode for process control, is mainly used to adjust the VFD output
frequency or output voltage by performing scale-division, integral and differential operations on
the difference between feedback signal of controlled variables and signal of the target, thus
forming a negative feedback system to keep the controlled variables above the target. It is
applicable to flow control, pressure control, temperature control, and so on. The following is
the basic schematic block diagram for output frequency regulation.

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