Configuration CP3003-SA
Page 4 - 10 ID 1052-6929, Rev. 3.0
D R A F T — F O R I N T E R N A L U S E O N L Y
4.2.7 Board Interrupt Configuration Register (BICFG)
The Board Interrupt Configuration Register holds a series of bits defining the interrupt routing.
Table 4-9: Board Interrupt Configuration Register (BICFG)
REGISTER NAME BOARD INTERRUPT CONFIGURATION REGISTER (BICFG)
ADDRESS 0x286
BIT NAME DESCRIPTION
RESET
VALUE
ACCESS
7 UICF UART IRQ3 and IRQ4 interrupt configuration:
0 = IRQ3 and IRQ4 interrupt disabled
1 = IRQ3 and IRQ4 interrupt enabled
1R/W
6 CFICF CPCI fail signal interrupt configuration (FAL signal):
0 = IRQ5 disabled
1 = IRQ5 enabled
0R/W
5 CEICF CPCI enumeration signal interrupt configuration (ENUM signal):
0 = IRQ5 disabled
1 = IRQ5 enabled
0R/W
4 CDICF CPCI derate signal interrupt configuration (DEG signal):
0 = IRQ5 disabled
1 = IRQ5 enabled
0R/W
3 - 2 Res. Reserved 00 R
1 - 0 WICF Watchdog interrupt configuration:
00 = Disabled
01 = IRQ5
10 = Reserved
11 = Reserved
00 R/W