This document contains proprietary information of KVH Industries, Inc. and neither this document nor said proprietary information shall be
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representative.
In the timing diagrams below, the Intermediate Data Available timing represented by the
higher speed internal sampling rates as data (D1, D2, D3, etc.) is updated internally. The
Output Request represents the signal to the system that output of data to the user is
requested. This may either be from an internal clocked signal or the external MSYNC signal.
____ ______________________ ___________________
Intermediate ____X________D1____________X_______D2__________
Data Available | |
|<-------- T1 -------->|<-- T2 -->|
|_____
Output Request ______________________________________| |____
As seen in the diagram above, the output request is asking for data at time T2 after sample
D2 becomes available, since its leading edge occurs after D2. However, no data is available
for that point in time yet since D2 is the latest data available. Therefore, the system instead
makes a translation in time to output data associated with the time T2 after D1 (one internal
sample prior). This is followed by linear interpolation between the D1 and D2 data to derive a
value between them. The timing diagram below shows how the system interprets the output
request signal.
____ ______________________ ___________________
Intermediate ____X________D1____________X_______D2__________
Data Available | |
|<-------- T1 -------->|
|<-- T2 -->|
|____
Output Request _______________| |__________________________
If time T2 is nearly 0, then even though the D2 values would be available, we would output
virtually nothing of them and instead output data primarily based on the D1 values. As time
T2 increases, we would output more and more of D2 and less of D1. We would thus maintain
the output of data at one internal sample period delay.
The alternatives to this would be to simply output the newest data available or, possibly to
attempt prediction of the output based on the past history. In the first case, we would end up
with an output timing variation of zero to as much as one internal data sample period as the
time T2 varied from 0 to T1. The use of interpolation mitigates this output uncertainty (jitter).
In the second, predictive case, there is less latency and justification to do this might be if the
error can be bounded by the filtering used and how far out in time the prediction is made.
However, the result is technically non-causal, since we cannot be certain of the value at a
time in the future.
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