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LSIS XEC-DR32H - Page 161

LSIS XEC-DR32H
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Chapter 9 Installation and Wiring
(3) Fail safe countermeasure in case of PLC error
Error of PLC CPU and memory is detected by self diagnosis but in case error occurs in IO control part, etc.,
CPU can detect the error. At this case, though it is different according to status of error, all contact point is on or
off, so safety may not be guaranteed. Though we do out best to our quality as producer, configure safety circuit
preparing that error occurs in PLC and it lead to breakdown or accident.
System example
Main
unit
Input
16
point
Input
16
point
Input
16
point
Input
16
point
Output
16
point
Output
16
point
Equip output module for fail safe to last slot of system.
[Fail safe circuit example]
Since P80 turn on/off every 0.5s, use TR output.
F0093
P80
P80
0.5s
0.5s
P80
P81
~
P8F
24V
0V
T1 T2
MC
-
+
DC24
MC
T1
T2
L
L
External load
CPU unit
Output module
On delay timer
Off delay timer
Output module for fail safe
서식 있음:
들여쓰기: 왼쪽 1.17
글자
서식 있는
서식 있음:
가운데
서식 있음:
간격: 1줄
서식 있음:
들여쓰기: 줄: 0 cm
서식 있음:
들여쓰기: 줄: 0 cm
서식 있음:
본문설명5, 들여쓰기:
줄: 0 cm, 왼쪽 0 글자
서식 있음:
들여쓰기: 왼쪽: 0 cm,
줄: 0 cm
서식 있음:
들여쓰기: 왼쪽: 0 cm,
줄: 0 cm
9 5

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