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Mitsubishi Electric MELSEC iQ-R Series - Page 447

Mitsubishi Electric MELSEC iQ-R Series
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APPENDICES APPENDIX
Appendix 1 Read/Write by Device Extension Specification
445
A
For CPU No.4 (start input/output number: 3E30H)
Indirect specification of the start input/output number of the CPU module can also be performed by using the
CPU module index register.
Page 446 Access to index the network No. and start input/output number
Device code and device number
Specify the following devices. (Page 67 Devices)
CPU buffer memory access device (G)
CPU buffer memory access device (HG)
For the values of device codes, refer to the following section.
Page 70 Device code list
Using the index register of CPU module, the access target device number can be specified indirectly.
Page 447 Access to index the device number
Device extension specification example
Access the buffer memory (address: 1) of the CPU No.1 (start input/output number: 03E0H) by specifying the subcommand
0082.
Data communication in ASCII code
Data communication in binary code
ASCII code Binary code
U
55
H
3
33
H
E
45
H
3
33
H
E3
H
03
H
00
30
H
30
H
55
H
33
H
45
E
30
H
30
H
30
H
30
H
30
H
47
H
2A
H
2A
H
2A
H
30
H
00
30
H
30
H
82
38
H
32
H
U3 00E 00000000010000
30
H
30
H
30
H
30
H
000G***
30
H
30
H
31
H
30
H
30
H
30
H
30
H
30
H
30
H
Device
code
Subcommand
Extension
specification
Device number
82
H
00
H
00
H
00
H
01
H
00
H
00
H
00
H
AB
H
00
H
00
H
00
H
E0
H
03
H
FA
H
Subcommand
Device
code
Device number
Extension
specification

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