NCR RealPOS 70 - Page 247

Chapter 12: Cash Drawer Interface 12-7
WithintheICH4,theGeneralPurposeI/Oportsareaddressedusingan
offsetreadfromtheGPIOBaseAddressRegister,[GPIOBASE](offset
0x58).ThebaseaddressincludedinBits[15:6]isassignedbytheBIOS.
TheGPIOControlRegister[GPIO_CNTL](offset0x5C)hasaR/Wbit
[4]thatenables(1)/disables(0)thedecode
oftheI/Orangepointedtoby
theGPIOBaseregisterandenables/disablestheGPIOfunction.The
GPIOControlRegisterissetbytheBIOStoenableGPIO.
Intel® 82801DB ICH4 Datasheet
GPIO_USE_SEL2—GPIO Use Select 2 Register
Offset Address: GPIOBASE +30h Attribute: R/W
Default Value: 00000FFFh Size: 32-bit
Lockable: No Power Well: Core
Bit Description
31:0
GPIO_USE_SEL2[43:32]—R/W.Eachbitinthisregisterenablesthe
correspondingGPIO(ifitexists)tobeusedasaGPIO,ratherthanfor
thenativefunction.
0=Signalusedasnativefunction.
1=SignalusedasaGPIO.
For7402,cashdrawerbitsGPIO_USE_SEL2[35:32]willbeset
=1for
useasaGPIO,writevalue=readvalueANDedwith0xF.
Afterafullreset(RSMRST#)allmultiplexedsignalsintheresumeand
corewellsareconfiguredastheirnativefunctionratherthanasa
GPIO.AfterjustaPCIRST#,theGPIOinthecorewellare
configuredas
theirnativefunction.
LPC Interface Bridge Registers (D31:F0)
GP_IO_SEL2—GPIO Input/Output Select 2 Register
Offset Address: GPIOBASE +34h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Lockable: No Power Well: Core