Nuvoton NuMicro MS51PC0AE - Features

MS51
Nov. 28, 2019 Page 11 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
2 FEATURES
Core and System
8051
 Fully static design 8-bit high performance 1T 8051-based
CMOS microcontroller.
 Instruction set fully compatible with MCS-51.
 4-priority-level interrupts capability.
 Dual Data Pointers (DPTRs).
Brown-out Detector (BOD)
 4-level selection, with brown-out interrupt and reset option.
(4.4V / 3.7V / 2.7V / 2.2V)
Low Voltage Reset (LVR)
 LVR with 2.0V threshold voltage level
Security
 96-bit Unique ID (UID)
 128-bit Unique Customer ID (UCID)
 128-bytes security protection memory SPROM
Memories
Flash
 Up to 32 KBytes of APROM for User Code.
 4/3/2/1 Kbytes of Flash for loader (LDROM) configure from
APROM for In-System-Programmable (ISP)
 Flash Memory accumulated with pages of 128 Bytes from
APROM by In-Application-Programmable (IAP) means whole
APROM can be use as Data Flash
 An additional 128 bytes security protection memory SPROM
 Code lock for security by CONFIG
SRAM
 256 Bytes on-chip RAM.
 Additional 2 KBytes on-chip auxiliary RAM (XRAM) accessed
by MOVX instruction.
Clocks
External Clock Source
 4~24 MHz High-speed external crystal oscillator (HXT) for
precise timing operation
Internal Clock Source
 Default 16 MHz high-speed internal oscillator (HIRC) trimmed
to ±1% (accuracy at 25 °C, 3.3 V), ±2% in -20~105°C.
 Selectable 24 MHz high-speed internal oscillator (HIRC).
 10 kHz low-speed internal oscillator (LIRC) calibrating to ±1%