Nuvoton NuMicro MS51PC0AE - Figure 6.11-13 Flow and Status of General Call Mode

MS51
Nov. 28, 2019 Page 417 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
S
I2CnDAT
(SLA+W=0x00)
ACK
(STA,STO,SI,AA)=(0,0,1,1)
GC=1
STATUS=0x70
I2CnDAT
(Data)
ACK
NAK
(STA,STO,SI,AA)=(0,0,1,1)
...
I2CnDAT
(Data)
(STA,STO,SI,AA)=(0,0,1,0)
STATUS=0x90
STATUS=0x98
S
(STA,STO,SI,AA)=(1,0,1,1)
... ...
Switch to not addressed mode
Own SLA will be recognized
Send START when bus free
S
(STA,STO,SI,AA)=(1,0,1,0)
... ...
Switch to not addressed mode
Own SLA will not be recognized
Send START when bus free
...
Switch to not addressed mode
Address 0x0 will be recognized
(STA,STO,SI,AA)=(0,0,1,0)
Switch to not addressed mode
Own SLA will not be recognized
Become I
2
C Master
Become I
2
C Master
Bus Free
...
(STA,STO,SI,AA)=(0,0,1,1)
Switch to not addressed mode
Own SLA will be recognized
Become I
2
C Slave
(Arbitration Lost)
STATUS=0x78
Arbitraion Lost
Master to Slave
Slave to Master
STATUS=0xA0
Sr
STATUS=0xA0
P
Sr
(STA,STO,SI,AA)=(0,0,1,1)
...
Sr
(STA,STO,SI,AA)=(0,0,1,X)
(STA,STO,SI,AA)=(0,0,1,X)
I2CnDAT
(SLA+W=0x00)
ACK
Figure 6.11-13 Flow and Status of General Call Mode
Miscellaneous States 6.11.2.6
There are two I2CnSTAT status codes that do not correspond to the 25 defined states, The first status
code F8H indicates that no relevant information is available during each transaction. Meanwhile, the
SI flag is 0 and no I
2
C interrupt is required. The other status code 00H means a bus error has occurred
during a transaction. A bus error is caused by a START or STOP condition appearing temporally at an
illegal position such as the second through eighth bits of an address or a data byte, and the
acknowledge bit. When a bus error occurs, the SI flag is set immediately. When a bus error is
detected on the I
2
C bus, the operating device immediately switches to the not addressed salve mode,
releases I2C0_SDA and I2C0_SCL lines, sets the SI flag, and loads I2CnSTAT as 00H. To recover
from a bus error, the STO bit should be set and then SI should be cleared. After that, STO is cleared
by hardware and release the I
2
C bus without issuing a real STOP condition waveform on I
2
C bus.