Nuvoton NuMicro MS51PC0AE - Table 10.1-2 Instruction Set

MS51
Nov. 28, 2019 Page 489 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
Instruction
OPCODE
Bytes
Clock
Cycles
MS51 V.S. Tradition
80C51 Speed Ratio
ORL C, bit
72
2
3
8
ORL C, /bit
A0
2
3
8
MOV C, bit
A2
2
3
4
MOV bit, C
92
2
4
6
ACALL addr11
11, 31, 51, 71, 91, B1, D1, F1
[2]
2
4
6
LCALL addr16
12
3
4
6
RET
22
1
5
4.8
RETI
32
1
5
4.8
AJMP addr11
01, 21, 41, 61, 81, A1, C1, E1
[3]
2
3
8
LJMP addr16
02
3
4
6
SJMP rel
80
2
3
8
JMP @A+DPTR
73
1
3
8
JZ rel
60
2
3
8
JNZ rel
70
2
3
8
JC rel
40
2
3
8
JNC rel
50
2
3
8
JB bit, rel
20
3
5
4.8
JNB bit, rel
30
3
5
4.8
JBC bit, rel
10
3
5
4.8
CJNE A, direct, rel
B5
3
5
4.8
CJNE A, #data, rel
B4
3
4
6
CJNE Rn, #data, rel
B8~BF
3
4
6
CJNE @Ri, #data, rel
B6, B7
3
6
4
DJNZ Rn, rel
D8~DF
2
4
6
DJNZ direct, rel
D5
3
5
4.8
Note：
[1] The MS51 does not have external memory bus. MOVX instructions are used to access internal XRAM.
[2] The most three significant bits in the 11-bit address [A10:A8] decide the ACALL hex code. The code will be
[A10,A9,A8,1,0,0,0,1].
[3] The most three significant bits in the 11-bit address [A10:A8] decide the AJMP hex code. The code will be
[A10,A9,A8,0,0,0,0,1].
Table 11.2-1 Instruction Set