Nuvoton NuMicro MS51PC0AE - Table 6.1-2 SFR Definitions and Reset Values

MS51
Nov. 28, 2019 Page 47 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
Register
Definition
Address
Page
MSB
7
6
5
4
3
2
1
LSB
[1]
0
Reset
Value
[2]
TA
P2SR
Port 2 Slew Rate
Control
8BH
2
P2SR.7
P2SR.6
P2SR.5
P2SR.4
P2SR.3
P2SR.2
P2SR.1
P2SR.0
0000 0000b
TL0
Timer 0 low byte
8AH
0
TL1[7:0]
0000 0000b
-
-
8AH
1
-
-
-
-
-
-
-
-
-
P2M2
P2 Mode Select 2
8AH
2
P2M2.7
P2M2.6
P2M2.5
P2M2.4
P2M2.3
P2M2.2
P2M2.1
P2M2.0
0000 0000b
TMOD
89H
0
0000 0000b
-
-
89H
1
-
-
-
-
-
-
-
-
-
P2M1
P2 Mode Select 1
89H
2
P2M1.7
P2M1.6
P2M1.5
P2M1.4
P2M1.3
P2M1.2
P2M1.1
P2M1.0
0000 0000b
TCON
Timer 0 and 1control
88H
A
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
0000 0000b
PCON
Power control
87H
A
SMOD
SMOD0
-
POF
GF1
GF0
PD
IDL
POR,
0001 0000b
Others,
000U 0000b
RWKL
Self Wake-up Timer
reload low byte
86H
0
RWK[7:0]
0000 0000b
-
-
86H
1
-
-
-
-
-
-
-
-
-
ADCCON3
ADC Control 3
86H
2
-
-
HIE
CONT
ADCAQT2
ADCAQT1
ADCAQT0
SLOW
0000 0000b
RCTRIM1
Internal RC trim
value low byte
85H
0
-
-
HIRC24
-
-
HIRCTRIM.
0
0000 0000b
Y
-
-
85H
1
-
-
-
-
-
-
-
-
-
ADCBAH
ADC RAM Base
Address High byte
85H
2
-
-
-
-
ADCBA3
ADCBA2
ADCBA1
ADCBA0
0000 0000b
RCTRIM0
Internal RC trim
value high byte
84H
0
HIRCTRIM[8:1]
0000 0000b
Y
-
-
84H
1
-
-
-
-
-
-
-
-
-
ADCBAL
ADC RAM Base
Address Low Byte
84H
2
ADCBA[7:0]
0000 0000b
DPH
Data pointer high
byte
83H
A
DPTR[15:8]
0000 0000b
DPL
Data pointer low byte
82H
A
DPTR[7:0]
0000 0000b
SP
Stack pointer
81H
A
SP[7:0]
0000 0111b
P0
Port 0
80H
A
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Output latch,
1111 1111b
Input,
XXXX XXXXb
Note:
1. ( ) item means the bit address in bit-addressable SFRs.
2. Reset value symbol description. 0: logic 0; 1: logic 1; U: unchanged; C: see [5]; X: see [3], [6], and [7].
3. All I/O pins are default input-only mode (floating) after reset. Reading back P2.0 is always 0 if RPD (CONFIG0.2) remains
un-programmed 1. After reset ICE_DAT and ICE_CLK pin will keep quasi mode with pull high resister 600 LIRC clock before
change to input mode.
4. These SFRs have TA protected writing.
5. These SFRs have bits those are initialized according to CONFIG values after specified resets.
6. BOF reset value depends on different setting of CONFIG2 and VDD voltage level. Please check
7. BOS is a read-only flag decided by VDD level while brown-out detection is enabled.
Table 6.1-2 SFR Definitions and Reset Values