MS51
Nov. 28, 2019 Page 249 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
6.3 Flash Memory Control
6.3.1 In-Application-Programming (IAP)
Unlike RAM’s real-time operation, to update Flash data often takes long time. Furthermore, it is a quite
complex timing procedure to erase, program, or read Flash data. The MS51 carried out the Flash
operation with convenient mechanism to help user re-programming the Flash content by In-
Application-Programming (IAP). IAP is an in-circuit electrical erasure and programming method
through software.
After IAP enabling by setting IAPEN (CHPCON.0 with TA protected) and setting the enable bit in
IAPUEN that allows the target block to be updated, user can easily fill the 16-bit target address in
IAPAH and IAPAL, data in IAPFD, and command in IAPCN. Then the IAP is ready to begin by setting
a triggering bit IAPGO (IAPTRG.0). Note that IAPTRG is also TA protected. At this moment, the CPU
holds the Program Counter and the built-in IAP automation takes over to control the internal charge-
pump for high voltage and the detail signal timing. The erase and program time is internally controlled
disregard of the operating voltage and frequency. Nominally, a page-erase time is 5 ms and a byte-
program time is 23.5 μs. After IAP action completed, the Program Counter continues to run the
following instructions. The IAPGO bit will be automatically cleared. An IAP failure flag, IAPFF
(CHPCON.6), can be check whether the previous IAP operation was successful or not. Through this
progress, user can easily erase, program, and verify the Flash Memory by just taking care of pure
software.
IAP Commands
6.3.1.1
The MS51 provides a wide range of applications to perform IAP to APROM, LDROM, or CONFIG
bytes. The IAP action mode and the destination of the Flash block are defined by IAP control register
IAPCN.
IAPA[15:0]
{IAPAH, IAPAL}
Low-byte DID: 0000H
High-byte DID: 0001H
Low-byte DID
High-byte DID
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