Nuvoton NuMicro MS51PC0AE - Interrupt System; Table 6.2-3 Interrupt Vectors

MS51
Nov. 28, 2019 Page 230 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
6.2.6 Interrupt System
Overview 6.2.6.1
The purpose of the interrupt is to make the software deal with unscheduled or asynchronous events.
The MS51 has a four-priority-level interrupt structure with 24 interrupt sources. Each of the interrupt
sources has an individual priority setting bits, interrupt vector and enable bit. In addition, the interrupts
can be globally enabled or disabled. When an interrupt occurs, the CPU is expected to service the
interrupt. This service is specified as an Interrupt Service Routine (ISR). The ISR resides at a
predetermined address as shown in Table 6.2-3 Interrupt Vectors. When the interrupt occurs if
enabled, the CPU will vector to the respective location depending on interrupt source, execute the
code at this location, stay in an interrupt service state until the ISR is done. Once an ISR has begun, it
can be interrupted only by a higher priority interrupt. The ISR should be terminated by a return from
interrupt instruction RETI. This instruction will force the CPU return to the instruction that would have
been next when the interrupt occurred.
Source
Vector
Addess
Vector
Number
Source
Vector
Address
Vector
Number
Reset
0000H
-
Input capture interrupt
0063H
12
External interrupt 0
0003H
0
PWM0 interrupt
006BH
13
Timer 0 overflow
000BH
1
Fault Brake interrupt
0073H
14
External interrupt 1
0013H
2
Serial port 1 interrupt
007BH
15
Timer 1 overflow
001BH
3
Timer 3 overflow
0083H
16
Serial port 0 interrupt
0023H
4
Self Wake-up Timer interrupt
008BH
17
Timer 2 event
002BH
5
PWM1 interrupt
0093H
18
I
2
C status/timer-out interrupt
0033H
6
PWM2 interrupt
009BH
19
Pin interrupt
003BH
7
PWM3 interrupt
00A3H
20
Brown-out detection interrupt
0043H
8
SC0 interrupt
00ABH
21
SPI interrupt
004BH
9
SC1 interrupt
00B3H
22
WDT interrupt
0053H
10
SC2 interrupt
00BBH
23
ADC interrupt
005BH
11
Table 6.2-3 Interrupt Vectors
Enabling Interrupts 6.2.6.2
Each of individual interrupt sources can be enabled or disabled through the use of an associated
interrupt enable bit in the IE and EIE0 SFR. There is also a global enable bit EA bit (IE.7), which can
be cleared to disable all the interrupts at once. It is set to enable all individually enabled interrupts.
Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable
settings. Note that interrupts which occur when the EA bit is set to logic 0 will be held in a pending
state, and will not be serviced until the EA bit is set back to logic 1. All interrupt flags that generate