Nuvoton NuMicro MS51PC0AE - Table 6.2-5 Characteristics of each Interrupt Source

MS51
Nov. 28, 2019 Page 238 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
Interrupt Source
Vector
Address
Interrupt Flag(S)
Enable Bit
Natural
Priority
Priority Control
Bits
Power-Down
Wake-Up
SC1 interrupt
00B3H
ACERR+BGT+TERR+TBE+
RDA (SC1IS[4:0])
SC1IE
23
PSC1, PSC1H
No
SC2 interrupt
00BBH
ACERR+BGT+TERR+TBE+
RDA (SC2IS[4:0])
SC2IE
24
PSC2, PSC2H
No
Note:
1. While the external interrupt pin is set as edge triggered (Itx = 1), its own flag Iex will be automatically cleared if
the interrupt service routine (ISR) is executed. While as level triggered (Itx = 0), Iex follows the inverse of
respective pin state. It is not controlled via software.
2. TF0, TF1, or TF3 is automatically cleared if the interrupt service routine (ISR) is executed. On the contrary, be
aware that TF2 is not.
3. If level triggered is selected for pin interrupt channel n, PIFn flag reflects the respective channel state. It is not
controlled via software.
Table 6.2-5 Characteristics of Each Interrupt Source