Nuvoton NuMicro MS51PC0AE - Figure 6.6-2 PWM1;2;3 Block Diagram

MS51
Nov. 28, 2019 Page 321 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
PWM mode, mask output and PWM polarity. The last stage is a multiplexer of PWM1/2/3 output or I/O
function.
16-bit
up/down
counter
PWMn_CH0
PWMn_CH1
Pre-scalar
INTSEL[1:0], INTTYP[1:0]
(PWMnCON0[3:0])
PWMRUNn
CLRPWM
(PWMnCON0.4)
PWMnP
registers
LOAD (PWMnCON0.6)
PWMF
(PWMnCON0.5)
PWMnP buffer
PWMnC0 buffer
PWMnC0 Register
0-to-1
PWMn and
Fault Brake
output
control
PWMTYP
(PWMnCON1.4)
edge/center
Interrupt
select/type
PWMDIV0[2:0]
(PWMnCON1[2:0])
PnG0
PWMn interrupt
Brake event
(PWMn_BRAKE)
0
1
Timer 1 overflow
PWMCKS
(CKCON.6)
F
PWM
=
Counter
Matching(edgealigned)/
underflow(venter aligned)
F
SYS
clear counter
=
PWMnC1 buffer
PWMnC1 Register
PnG1
=
(PWMnPH,
PWMnPL)
(PWMnCH0H,
PWMnCH0L)
(PWMnCH1H,
PWMnCH1L)
Figure 6.6-2 PWM1/2/3 Block Diagram