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MS51
Nov. 28, 2019 Page 248 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
TCON Timer 0 and 1 Control
Register
SFR Address
Reset Value
TCON
88H, All pages, Bit-addressable
0000_0000b
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
R/W
R/W
R/W
R/W
R (level)
R/W (edge)
R/W
R (level)
R/W (edge)
R/W
Bit
Name
Description
3
IE1
External interrupt 1 edge flag
If IT1 = 1 (falling edge trigger), this flag will be set by hardware when a falling edge is detected. It
remain set until cleared via software or cleared by hardware in the beginning of its interrupt service
routine.
If IT1 = 0 (low level trigger), this flag follows the inverse of the INT1
input signal’s logic level.
Software cannot control it.
2
IT1
External interrupt 1 type select
This bit selects by which type that INT1
is triggered.
0 = INT1
is low level triggered.
1 = INT1
is falling edge triggered.
1
IE0
External interrupt 0 edge flag
If IT0 = 1 (falling edge trigger), this flag will be set by hardware when a falling edge is detected. It
remain set until cleared via software or cleared by hardware in the beginning of its interrupt service
routine.
If IT0 = 0 (low level trigger), this flag follows the inverse of the INT0
input signal’s logic level.
Software cannot control it.
0
IT0
External interrupt 0 type select
This bit selects by which type that INT0
is triggered.
0 = INT0
is low level triggered.
1 = INT0
is falling edge triggered.

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