Nuvoton NuMicro MS51PC0AE - Page 418

MS51
Nov. 28, 2019 Page 418 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
There is a special case if a START or a repeated START condition is not successfully generated for
I
2
C bus is obstructed by a low level on I2C0_SDA line e.g. a slave device out of bit synchronization,
the problem can be solved by transmitting additional clock pulses on the I2C0_SCL line. The I
2
C
hardware transmits additional clock pulses when the STA bit is set, but no START condition can be
generated because the I2C0_SDA line is pulled low. When the I2C0_SDA line is eventually released,
a normal START condition is transmitted, state 08H is entered, and the serial transaction continues. If
a repeated START condition is transmitted while I2C0_SDA is obstructed low, the I
2
C hardware also
performs the same action as above. In this case, state 08H is entered instead of 10H after a
successful START condition is transmitted. Note that the software is not involved in solving these bus
problems.
The following table is show the status display in I2STAT register of I
2
C number and description:
Master Mode
Slave Mode
STATUS
Description
STATUS
Description
0x08
Start
0Xa0
Slave Transmit Repeat Start or Stop
0x10
Master Repeat Start
0Xa8
Slave Transmit Address ACK
0x18
Master Transmit Address ACK
0Xb0
Slave Transmit Arbitration Lost
0x20
Master Transmit Address NACK
0Xb8
Slave Transmit Data ACK
0x28
Master Transmit Data ACK
0Xc0
Slave Transmit Data NACK
0x30
Master Transmit Data NACK
0Xc8
Slave Transmit Last Data ACK
0x38
Master Arbitration Lost
0x60
Slave Receive Address ACK
0x40
Master Receive Address ACK
0x68
Slave Receive Arbitration Lost
0x48
Master Receive Address NACK
0x80
Slave Receive Data ACK
0x50
Master Receive Data ACK
0x88
Slave Receive Data NACK
0x58
Master Receive Data NACK
0x70
GC mode Address ACK
0x00
Bus error
0x78
GC mode Arbitration Lost
0x90
GC mode Data ACK
0x98
GC mode Data NACK
0xF8
Bus Released
Note: Status “0xF8” exists in both master/slave modes, and it won’t raise interrupt.
6.11.3 Typical Structure of I
2
C Interrupt Service Routine
The following software example in C language for KEIL
TM
C51 compiler shows the typical structure of
the I
2
C interrupt service routine including the 26 state service routines and may be used as a base for
user applications. User can follow or modify it for their own application. If one or more of the five
modes are not used, the associated state service routines may be removed, but care should be taken
that a deleted routine can never be invoked.
Void I2C_ISR (void) interrupt 6
{
switch (I2STAT)
{
//===============================================
//Bus Error, always put in ISR for noise handling
//===============================================
case 0x00: /*00H, bus error occurs*/