MS51
Nov. 28, 2019 Page 258 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
IAPTRG – IAP Trigger
A4H, Page 0, TA protected
IAP go
IAP begins by setting this bit as logic 1. After this instruction, the CPU holds the Program Counter
(PC) and the IAP hardware automation takes over to control the progress. After IAP action
completed, the Program Counter continues to run the following instruction. The IAPGO bit will be
automatically cleared and always read as logic 0.
Before triggering an IAP action, interrupts (if enabled) should be temporary disabled for hardware
limitation.
The program process should follows below.
CLR EA
MOV TA,#0AAH
MOV TA,#55H
ORL IAPTRG,#01H
(SETB EA)
IAP User Guide 6.3.1.3
IAP facilitates the updating Flash contents in a convenient way; however, user should follow some
restricted laws in order that the IAP operates correctly. Without noticing warnings will possible cause
undetermined results even serious damages of devices. Furthermore, this paragraph will also support
useful suggestions during IAP procedures.
1. If no more IAP operation is needed, user should clear IAPEN (CHPCON.0). It will make the
system void to trigger IAP unaware. Furthermore, IAP requires the HIRC running. If the
external clock source is selected, disabling IAP will stop the HIRC for saving power
consumption. Note that a write to IAPEN is TA protected.
2. When the LOCK bit (CONFIG0.1) is activated, IAP reading, writing, or erasing can still be
valid.
During IAP progress, interrupts (if enabled) should be disabled temporally by clearing EA bit for
implement limitation.
Do not attempt to erase or program to a page that the code is currently executing. This will cause
unpredictable program behavior and may corrupt program data.
Using Flash Memory as Data Flash 6.3.1.4
In general application, there is a need of data storage, which is non-volatile so that it remains its
content even after the power is off. Therefore, in general application user can read back or update the
data, which rules as parameters or constants for system control. The Flash Memory array of the MS51
To Next Page
Loading...
