Nuvoton NuMicro MS51PC0AE - Page 358

MS51
Nov. 28, 2019 Page 358 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
WDCON – Watchdog Timer Control
Register
SFR Address
Reset Value
WDCON
AAH, Page 0, TA protected
POR 0000_0111 b
WDT 0000_1UUU b
Others 0000_UUUU b
7
6
5
4
3
2
1
0
WDTR
WDCLR
WDTF
WIDPD
WDTRF
WDPS[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
7
WDTR
WDT run
This bit is valid only when control bits in WDTEN[3:0] (CONFIG4[7:4]) are all 1. At this time, WDT
works as a general purpose timer.
0 = WDT Disabled.
1 = WDT Enabled. The WDT counter starts running.
6
WDCLR
WDT clear
Setting this bit will reset the WDT count to 00H. It puts the counter in a known state and prohibit
the system from unpredictable reset. The meaning of writing and reading WDCLR bit is different.
Writing:
0 = No effect.
1 = Clearing WDT counter.
Reading:
0 = WDT counter is completely cleared.
1 = WDT counter is not yet cleared.
5
WDTF
WDT time-out flag
This bit indicates an overflow of WDT counter. This flag should be cleared by software.
4
WIDPD
WDT running in Idle or Power-down mode
This bit is valid only when control bits in WDTEN[3:0] (CONFIG4[7:4]) are all 1. It decides whether
WDT runs in Idle or Power-down mode when WDT works as a general purpose timer.
0 = WDT stops running during Idle or Power-down mode.
1 = WDT keeps running during Idle or Power-down mode.
3
WDTRF
WDT reset flag
When the CPU is reset by WDT time-out event, this bit will be set via hardware. This flag is
recommended to be cleared via software after reset.
2:0
WDPS[2:0]
WDT clock pre-scalar select
These bits determine the pre-scale of WDT clock from 1/1 through 1/256. See Table 6.7-1. The
default is the maximum pre-scale value.
Note:
1. WDTRF will be cleared after power-on reset, be set after WDT reset, and remains unchanged after any other
resets.
2. WDPS[2:0] are all set after power-on reset and keep unchanged after any reset other than power-on reset.