Nuvoton NuMicro MS51PC0AE - Page 427

MS51
Nov. 28, 2019 Page 427 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
I2CLK – I
2
C Clock
Register
SFR Address
Reset Value
I2CLK
BEH, Page 0
0000_1001 b
7
6
5
4
3
2
1
0
I2CLK[7:0]
R/W
Bit
Name
Description
7:0
I2CLK[7:0]
I
2
C clock setting
In master mode:
This register determines the clock rate of I
2
C bus when the device is in a master mode. The clock
rate follows the equation,
)1+CLK2I(×4
F
SYS
.
The default value will make the clock rate of I
2
C bus 400k bps if the peripheral clock is 16 MHz.
Note that the I2CLK value of 00H and 01H are not valid. This is an implement limitation.
In slave mode:
This byte has no effect. In slave mode, the I
2
C device will automatically synchronize with any
given clock rate up to 400k bps.