Nuvoton NuMicro MS51PC0AE - Page 45

MS51
Nov. 28, 2019 Page 45 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
Register
Definition
Address
Page
MSB
7
6
5
4
3
2
1
LSB
[1]
0
Reset
Value
[2]
TA
PWM1_C
H0H
PWM1 channel 0
duty high byte
ABH
2
PWM1_CH015:8]
0000 0000b
WDCON
Watchdog Timer
control
AAH
0
WDTR
WDCLR
WDTF
WIDPD
WDTRF
WDPS2
WDPS1
WDPS0
POR,
0000 0111b
WDT,
0000 1UUUb
Others,
0000 UUUUb
Y
-
-
AAH
1
-
-
-
-
-
-
-
-
-
PWM1PH
PWM1 period high
byte
AAH
2
PWM1P[15:8]
0000 0000b
SADDR
Slave 0 address
A9H
0
SADDR[7:0]
0000 0000b
-
-
A9H
1
-
-
-
-
-
-
-
-
-
PWM1PH
PWM1 period high
byte
A9H
2
PWM1P[15:8]
0000 0000b
IE
Interrupt enable
A8H
A
EA
EADC
EBOD
ES
ET1
EX1
ET0
EX0
0000 0000b
IAPAH
IAP address high
byte
A7H
0
IAPA[15:8]
0000 0000b
-
-
A7H
1
-
-
-
-
-
-
-
-
-
AUXR8
Auxiliary Register 8
A7H
2
CLODIV3
CLODIV2
CLODIV1
CLODIV0
CKTESTOE
N3
CKTESTOE
N2
CKTESTOE
N1
CKTESTOE
N0
0000 0000b
Y
IAPAL
IAP address low byte
A6H
0
IAPA[7:0]
0000 0000b
-
-
A6H
1
-
-
-
-
-
-
-
-
-
AUXR7
Auxiliary Register 7
A6H
2
-
-
-
SPI0NSSP
1
SPI0NSSP
0
SPI0MOSIP
SPI0MISOP
SPI0CKP
0000 0000b
IAPUEN
IAP update enable
A5H
0
-
-
SPMEN
SPUEN
CFUEN
LDUEN
APUEN
0000 0000b
Y
-
-
A5H
1
-
-
-
-
-
-
-
-
-
AUXR6
Auxiliary Register 6
A5H
2
-
-
-
UART4DG
UART3DG
UART2DG
UART1DG
UART0DG
0000 0000b
IAPTRG
IAP trigger
A4H
0
-
-
-
-
-
-
IAPGO
0000 0000b
Y
-
-
A4H
1
-
-
-
-
-
-
-
-
-
AUXR5
Auxiliary Register 5
A4H
2
CLOP
T0P
PWM3_CH
1P1
PWM3_CH
1P0
PWM3_CH
0P1
PWM3_CH
0P0
0000 0000b
BODCON
0
Brown-out detection
control 0
A3H
0
BODEN
-
BOV1
BOV0
BOF
BORST
BORF
BOS
POR,
CCCC XC0Xb
BOD,
UUUU XU1Xb
Others,
UUUU XUUXb
Y
-
-
A3H
1
-
-
-
-
-
-
-
-
-
AUXR4
Auxiliary Register 4
A3H
2
PWM2_CH
1P1
PWM2_CH
1P0
PWM2_CH
0P1
PWM2_CH
0P0
PWM1_CH
1P1
PWM1_CH
1P0
PWM1_CH
0P1
PWM1_CH
0P0
0000 0000b
AUXR1
Auxiliary register 1
A2H
0
SWRF
RSTPINF
HardF
SLOW
GF2
UART0PX
0
DPS
POR,
0000 0000b
Software,
1U00 0000b
nRESET pin,
U100 0000b
Others,
UUU0 0000b
-
-
A2H
1
-
-
-
-
-
-
-
-
-
AUXR3
Auxiliary Register 3
A2H
2
UART4TXP
1
UART4TXP
0
UART4RXP
1
UART4RXP
0
UART3TXP
1
UART3TXP
0
UART3RXP
1
UART3RXP
0
0000 0000b
-
-
A1H
0
-
-
-
-
-
-
-
-
-
-
-
A1H
1
-
-
-
-
-
-
-
-
-
AUXR2
Auxiliary Register 2
A1H
2
UART2TXP
1
UART2TXP
0
UART2RXP
1
UART2RXP
0
UART1TXP
1
UART1TXP
0
UART1RXP
1
UART1RXP
0
0000 0000b
P2
Port 2
A0H
A
-
-
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
Output latch,
0000 000Xb
Input,
0000 000Xb
CHPCON
Chip control
9FH
0
SWRST
IAPFF
-
-
-
-
BS[5]
IAPEN
Software,
0000 00U0b
Others,
0000 00C0b
Y
-
-
9FH
1
-
-
-
-
-
-
-
-
-
-
-
9FH
2
-
-
-
-
-
-
-
-
-
-
-
9EH
1
-
-
-
-
-
-
-
9EH
1
-
-
-
-
-
-
-
-
-
9EH
2
RSR
Reset Flag Register
9DH
0
-
-
HardF(mirro
red from
AUXR1.5)
POF
(mirrored
from
PCON.4)
RSTPINF
(mirrored
from
AUXR1.6)
BORF
(mirrored
from
BODCON0.
1)
WDTRF
(mirrored
from
WDCON.3)
SWRF
(mirrored
from
AUXR1.7)
00XX XXXXb
-
-
9DH
1
-
-
-
-
-
-
-
-
-