Nuvoton NuMicro MS51PC0AE - Page 463

MS51
Nov. 28, 2019 Page 463 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
ADCSR – ADC Status Register
Register
SFR Address
Reset Value
ADCSR
8FH, Page 2
0000_0000 b
7
6
5
4
3
2
1
0
-
-
-
-
-
CMPHIT
HDONE
FDONE
-
-
-
-
-
R/W
R/W
R/W
Bit
Description
[7:3]
Reserved
Reserved
[2]
CMPHIT
ADC comparator Hit Flag
This bit is set by hardware when ADCMPO (ADCCON2.4) flag rising
Note: This bit can be cleared by writing 0 to it.
[1]
HDONE
A/D Conversion Half Done Flag
This bit is set by hardware when half of ADCSN A/D conversions are complete in continue
mode.
Note: This bit can be cleared by writing 0 to it
[0]
FDONE
A/D Conversion Full Done Flag
This bit is set by hardware when all of ADCSN A/D conversions are complete in continue
mode or single conversion in single mode.
Note: This bit can be cleared by writing 0 to it..