Nuvoton NuMicro MS51PC0AE - Page 54

MS51
Nov. 28, 2019 Page 54 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
PCON – Power Control
Register
SFR Address
Reset Value
PCON
87H, All pages
POR: 0001_0000b
Others: 000U _0000b
7
6
5
4
3
2
1
0
SMOD
SMOD0
-
POF
GF1
GF0
PD
IDL
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
7
SMOD
Serial port 0 double baud rate enable
Setting this bit doubles the serial port baud rate when UART0 is in Mode 2 or when Timer 1
overflow is used as the baud rate source of UART0 Mode 1 or 3. See Table 6.9-1 Serial Port
UART0 Mode / baudrate Description for details.
6
SMOD0
Serial port 0 framing error flag access enable
0 = SCON.7 accesses to SM0 bit.
1 = SCON.7 accesses to FE bit.
4
POF
Power-on reset flag
This bit will be set as 1 after a power-on reset. It indicates a cold reset, a power-on reset complete.
This bit remains its value after any other resets. This flag is recommended to be cleared via
software.
3
GF1
General purpose flag 1
The general purpose flag that can be set or cleared by user via software.
2
GF0
General purpose flag 0
The general purpose flag that can be set or cleared by user via software.
1
PD
Power-down mode
Setting this bit puts CPU into Power-down mode. Under this mode, both CPU and peripheral clocks
stop and Program Counter (PC) suspends. It provides the lowest power consumption. After CPU is
woken up from Power-down, this bit will be automatically cleared via hardware and the program
continue executing the interrupt service routine (ISR) of the very interrupt source that woke the
system up before. After return from the ISR, the device continues execution at the instruction, which
follows the instruction that put the system into Power-down mode.
Note that If IDL bit and PD bit are set simultaneously, CPU will enter Power-down mode. Then it
does not go to Idle mode after exiting Power-down.
0
IDL
Idle mode
Setting this bit puts CPU into Idle mode. Under this mode, the CPU clock stops and Program
Counter (PC) suspends but all peripherals keep activated. After CPU is woken up from Idle, this bit
will be automatically cleared via hardware and the program continue executing the ISR of the very
interrupt source that woke the system up before. After return from the ISR, the device continues
execution at the instruction which follows the instruction that put the system into Idle mode.