Table 40. DSPI CMOS master classic timing (full duplex and output only) - MTFE = 0, CPHA
= 0 or 1 (continued)
# Symbol Characteristic Condition Value
1
Unit
Pad drive
2
Load (C
L
) Min Max
SCK = 50 pF
4 t
SDC
SCK duty cycle
6
SCK drive strength
Very strong 0 to 50 pF
1
/
2
t
SCK
- 2
1
/
2
t
SCK
+ 2 ns
Strong 0 to 50 pF
1
/
2
t
SCK
- 2
1
/
2
t
SCK
+ 2
Medium 0 to 50 pF
1
/
2
t
SCK
- 5
1
/
2
t
SCK
+ 5
PCS strobe timing
5 t
PCSC
PCSx to PCSS time
,
7
PCS and PCSS drive strength
Strong 25 pF 13.0 — ns
6 t
PASC
PCSS to PCSx time
7
PCS and PCSS drive strength
Strong 25 pF 13.0 — ns
SIN setup time
7 t
SUI
SIN setup time to
SCK
8
SCK drive strength
Very strong 25 pF 25.0 — ns
Strong 50 pF 31.0 —
Medium 50 pF 52.0 —
SIN hold time
8 t
HI
SIN hold time from
SCK
8
SCK drive strength
Very strong 0 pF -1.0 — ns
Strong 0 pF -1.0 —
Medium 0 pF -1.0 —
SOUT data valid time (after SCK edge)
9 t
SUO
SOUT data valid time
from SCK
9
SOUT and SCK drive strength
Very strong 25 pF — 7.0 ns
Strong 50 pF — 8.0
Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
10 t
HO
SOUT data hold time
after SCK
9
SOUT and SCK drive strength
Very strong 25 pF -7.7 — ns
Strong 50 pF -11.0 —
Medium 50 pF -15.0 —
1. All timing values for output signals in this table are measured to 50% of the output voltage.
2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
4. t
SYS
is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min t
SYS
= 10
ns).
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
NXP Semiconductors 67
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