MPC5777M Microcontroller Data Sheet, Rev. 6
Document revision history
NXP Semiconductors142
2 4/2013
Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics
(con’t)
Table 20 (Reset electrical characteristics)
• New specification: W
FNMI
(ESR1 input filtered pulse)
• New specification: W
NFNMI
(ESR1 input not filtered pulse)
• New specification: V
DD_POR
(Minimum supply for strong pull-down activation)
•I
OL_R
condition changed (V
DD_HV_IO
= 1.0 V is now V
DD_HV_IO
=V
DD_POR
, V
DD_HV_IO
= 4.0 V is now 3.0 V < V
DD_HV_IO
< 5.5 V, and V
OL
= 0.35*V
DD_HV_IO
is now V
OL
>
0.9 V)
• Specification change: I
OL_R
(3.0 V < V
DD_HV_IO
< 5.5 V, V
OL
> 0.9 V) min value is
11 mA (was 15)
• Added footnote: An external 4.7 K pull-up resistor is recommended to be used with
the PORST and ESR0 pins for fast negation of the signals.
• Added footnote: I
OL_R
applies to both PORST and ESR0: Strong pull-down is active on
PHASE0 for PORST. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and
the beginning of PHASE3 for ESR0.
• Added note on reset signal slew rate restrictions
Electrical characteristics—Oscillator and FMPLL
Section 3.12, Oscillator and FMPLL
Table 21 (PLL0 electrical characteristics)
• New specification: f
PLL0PHI0
(PLL0 output frequency)
• Specification change: t
PLL0LOCK
(PLL0 lock time) maximum is 100 µs (was
100–110 µs)
•
PLL0LTJ
specification parameter and conditions change: “PLL0 output long term jitter,
f
PLL0IN
= 20 MHz (resonator), VCO frequency = 800 MHz” (was “PLL0 output long term
jitter, f
PLL0IN
= 20 MHz (resonator)”). Conditions significantly revised.
• Revised footnote: “VDD_LV noise due to application in the range V
DD_LV
= 1.25 V ±5%
with frequency below PLL bandwidth (40 KHz) will be filtered” (was “1.25 V ±5%
application noise below 40kHz at VDD_LV pin”)
• Removed “F” from “FXOSC” in footnote 1
Table 22 (PLL1 electrical characteristics)
• Specification change: f
PLL1PHI
(PLL1 output clock PHI) is now f
PLL1PHI0
(PLL1 output
clock PHI0)
• Specification change: f
PLL1PHI0
(PLL1 output clock PHI0) max is 200 MHz (was
625 MHz)
•f
PLL1PHI parameter, Max column, changed 200MHz to 300MHz.
• Removed “F” from “FXOSC” in footnote 1
Table 76. Revision history (continued)
Revision Date Description of changes
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