NXP Semiconductors MPC5777M - Page 160

MPC5777M Microcontroller Data Sheet, Rev. 6
Document revision history
NXP Semiconductors160
3 3/2014
Electrical characteristics—AC specifications—Fast Ethernet Controller (FEC)
Table 61 (MII serial management channel timing):
• Added footnote to “Value” column: “Output parameters are valid for C
L
=25pF, where
C
L
is the external load to the device. The internal package capacitance is accounted
for, and does not need to be subtracted from the 25 pF value.”
Table 63 (RMII transmit signal timing,):
• Added footnote to “Value” column “Output parameters are valid for C
L
= 25 pF, where
C
L
is the external load to the device. The internal package capacitance is accounted
for, and does not need to be subtracted from the 25 pF value.”
• Added footnote to table title: “RMII timing is valid only up to a maximum of 150
o
C
junction temperature.”
Electrical characteristics—AC specifications—FlexRay
Section 3.16.4, FlexRay timing:
• Removed reference to “292 MAPBGA”.
• Removed “ . . . and subject to change per the final timing analysis of the device” from
FlexRay specification sentence.
Table 66 (RxD input characteristics):
• Added footnote: “FlexRay RxD timing is valid for all input levels and hysteresis
disabled."
Electrical characteristics—AC specifications—EBI
Table 69 (Bus Operation Timing):
• Changed bus frequency in table heading to “66.7 MHz” (was “66 MHz”).
• Footnote 1, added "with DSC = 0b10 for ADDR/CTRL and DSC = 0b11 for
CLKOUT/DATA."
• Footnote 3, changed “[Clock Register TBD]” TO “CGM_SC_DC4 register”.
• Footnote 4, changed "VDDE" to "VDD_HV_IO_EBI or VDD_HV_IO_FLEXE."
• Spec 5, Characteristic column, added “ADDR[8:11]/WE
[0:3]/BE[0:3],” “BDIP,” and
overbar on CS, OE, and TS. Changed "ADDR[8:31]" to "ADDR[12:31]."
• Spec 6, Characteristic column, added “ADDR[8:11]/WE
[0:3]/BE[0:3]”, “BDIP,” overbar
on CS, OE, TS, and footnote “One wait state must be added to the output signal valid
delay for external writes.” Changed "ADD[8:31]" to "ADDR[12:31]."
• Spec 7, change Min value from “6.0” to “7.0” ns.
• Spec 8, Characteristic column, changed to “DATA[0:31]”.
• Removed cut 1 footnotes associated with output delay and setup time (total 2).
Figure 50 (D_CLKOUT Timing)
Figure 51 (Synchronous Output Timing)
Figure 52 (Synchronous Input Timing):
• Changed “VDDE” to “VDD_HV_IO_EBI” throughout.
Electrical characteristics—AC specifications—I2C
Section 3.16.8, “I2C timing:
New section.
Electrical characteristics—AC specifications—GPIO delay
Section 3.19.10, GPIO delay timing
• New section
Table 76. Revision history (continued)
Revision Date Description of changes