Connectivity line devices: reset and clock control (RCC) RM0008
127/1128 DocID13902 Rev 15
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz.
All peripheral clocks are derived from the system clock (SYSCLK) except:
• The Flash memory programming interface clock (FLITFCLK) is always the HSI clock
• The USB OTG FS 48 MHz clock which is derived from the PLL VCO clock (2 ×
PLLCLK), followed by a programmable prescaler (divide by 3 or 2). This selection is
made through the OTGFSPRE bit in the RCC_CFGR register. For proper USB OTG FS
operation, the PLL should be configured to output 72 MHz or 48 MHz.
• The I2S2 and I2S3 clocks which can be derived from the system clock (SYSCLK) or
the PLL3 VCO clock (2 × PLL3CLK). This selection is made through the I2SxSRC bit in
the RCC_CFGR2 register. For more information on PLL3 and how to configure the I2S
clock to achieve high-quality audio performance, please refer to Section 25.4.3: Clock
generator.
• The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external
PHY. For further information on the Ethernet configuration, please refer to
Section 29.4.4: MII/RMII selection.
When the Ethernet is used, the AHB clock frequency must be at least 25 MHz.
The RCC feeds the Cortex
®
System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex
®
clock
(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by
the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The timer clock frequencies are automatically fixed by hardware. There are two cases:
1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the
timers are connected.
FCLK acts as Cortex
®
-M3’s free-running clock. For more details refer to the ARM Cortex™-
M3 r1p1 Technical Reference Manual (TRM).
8.2.1 HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
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