DocID13902 Rev 15 224/1128
RM0008 Analog-to-digital converter (ADC)
252
11.6 Channel-by-channel programmable sample time
ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us-
ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be
sampled with a different sample time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12.5 cycles
Example:
With an ADCCLK = 14 MHz and a sampling time of 1.5 cycles:
Tconv = 1.5 + 12.5 = 14 cycles = 1 µs
11.7 Conversion on external trigger
Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXT-
TRIG control bit is set then external events are able to trigger a conversion. The EXT-
SEL[2:0] and JEXTSEL[2:0] control bits allow the application to select decide which out of 8
possible events can trigger conversion for the regular and injected groups.
Note: When an external trigger is selected for ADC regular or injected conversion, only the rising
edge of the signal can start the conversion.
Table 67. External trigger for regular channels for ADC1 and ADC2
Source Type EXTSEL[2:0]
TIM1_CC1 event
Internal signal from on-chip
timers
000
TIM1_CC2 event 001
TIM1_CC3 event 010
TIM2_CC2 event 011
TIM3_TRGO event 100
TIM4_CC4 event 101
EXTI line 11/TIM8_TRGO
event
(1)(2)
1. The TIM8_TRGO event exists only in high-density and XL-density devices.
2. The selection of the external trigger EXTI line11 or TIM8_TRGO event for regular channels is done through
configuration bits ADC1_ETRGREG_REMAP and ADC2_ETRGREG_REMAP for ADC1 and ADC2,
respectively.
External pin/Internal signal from
on-chip timers
110
SWSTART Software control bit 111
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