Flexible static memory controller (FSMC) RM0008
507/1128 DocID13902 Rev 15
Table 108. NOR Flash/PSRAM controller: example of supported memories
and transactions
Device Mode R/W
AHB
data
size
Memory
data size
Allowed/
not
allowed
Comments
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
Asynchronous R 8 16 Y
Asynchronous W 8 16 N
Asynchronous R 16 16 Y
Asynchronous W 16 16 Y
Asynchronous R 32 16 Y Split into 2 FSMC accesses
Asynchronous W 32 16 Y Split into 2 FSMC accesses
Asynchronous
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R - 16 N Mode is not supported
Synchronous R 8 16 N
Synchronous R 16 16 Y
Synchronous R 32 16 Y
PSRAM
(multiplexed
I/Os and
nonmultiplexed
I/Os)
Asynchronous R 8 16 Y
Asynchronous W 8 16 Y Use of byte lanes NBL[1:0]
Asynchronous R 16 16 Y
Asynchronous W 16 16 Y
Asynchronous R 32 16 Y Split into 2 FSMC accesses
Asynchronous W 32 16 Y Split into 2 FSMC accesses
Asynchronous
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R - 16 N Mode is not supported
Synchronous R 8 16 N
Synchronous R 16 16 Y
Synchronous R 32 16 Y
Synchronous W 8 16 Y Use of byte lanes NBL[1:0]
Synchronous W 16/32 16 Y
SRAM and
ROM
Asynchronous R 8 / 16 16 Y
Asynchronous W 8 / 16 16 Y Use of byte lanes NBL[1:0]
Asynchronous R 32 16 Y Split into 2 FSMC accesses
Asynchronous W 32 16 Y
Split into 2 FSMC
accesses.
Use of byte lanes NBL[1:0]
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