ST STM32F105 series User Manual

General-purpose timers (TIM9 to TIM14) RM0008
439/1128 DocID13902 Rev 15
16.4.2 9/12TIM9/12 slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
1514131211109876543210
Reserved
TS[2:0]
Res.
SMS[2:0]
rw rw rw rw rw rw
Bits 6:4 TS: Trigger selection
This bitfield selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Internal Trigger 2 (ITR2)
011: Internal Trigger 3 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: Reserved.
See Table 89: TIMx internal trigger connection on page 439 for more details on the meaning
of ITRx for each timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMS: Slave mode selection
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input control register and Control register
descriptions.
000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal
clock
001: Reserved
010: Reserved
011: Reserved
100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers
101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops
are both controlled
110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled
111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter
Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
Gated mode checks the level of the trigger signal.
Table 89. TIMx internal trigger connection
Slave TIM ITR0 (TS =’ 000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ’011’)
TIM2 TIM1 TIM8 TIM3 TIM4
TIM3 TIM1 TIM2 TIM5 TIM4

ST STM32F105 series Specifications

General

Brand	ST
Model	STM32F105 series
Category	Microcontrollers
Language	English