DocID13902 Rev 15 754/1128
RM0008 Inter-integrated circuit (I
2
C) interface
777
Figure 273. Method 1: transfer sequence diagram for master receiver
1. If a single byte is received, it is NA.
2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.
3. The EV7 software sequence must complete before the end of the current byte transfer. In case EV7 software sequence can
not be managed before the current byte end of transfer, it is recommended to use BTF instead of RXNE with the drawback
of slowing the communication.
4. The EV6_1 or EV7_1 software sequence must complete before the ACK pulse of the current byte transfer.
Method 2: This method is for the case when the I2C is used with interrupts that do not have
the highest priority in the application or when the I2C is used with polling.
With this method, DataN_2 is not read, so that after DataN_1, the communication is
stretched (both RxNE and BTF are set). Then, clear the ACK bit before reading DataN-2 in
DR to ensure it is be cleared before the DataN Acknowledge pulse. After that, just after
reading DataN_2, set the STOP/ START bit and read DataN_1. After RxNE is set, read
DataN. This is illustrated below:
BITMASTERRECEIVER
BITMASTERRECEIVER
,EGEND33TART3
R
2EPEATED3TART03TOP!!CKNOWLEDGE.!.ONACKNOWLEDGE
%6X%VENTWITHINTERRUPTIF)4%6&%.
%63"CLEAREDBYREADING32REGISTERFOLLOWEDBYWRITING$2REGISTER
%6!$$2CLEAREDBYREADING32REGISTERFOLLOWEDBYREADING32)NBITMASTERRECEIVERMODETHISSE
QUENCESHOULDBEFOLLOWEDBYWRITING#2WITH34!24
%62X.%CLEAREDBYREADING$2REGISTER
%6?2X.%CLEAREDBYREADING$2REGISTERPROGRAM!#+AND34/0REQUEST
%6!$$CLEAREDBYREADING32REGISTERFOLLOWEDBYWRITING$2REGISTER
3 !DDRESS ! $ATA !
$ATA !
$ATA. .! 0
%6 %6 %6 %6 %6? %6
3 (EADER ! !DDRESS !
%6 %6 %6
3
R
(EADER !
$ATA !
%6
%6 %6
%6?
%6?NOASSOCIATEDFLAGEVENTUSEDFORBYTERECEPTIONONLY4HE!CKNOWLEDGEDISABLEAND3TOPCONDITION
GENERATIONAREMADEJUSTAFTER%6THATISAFTER!$$2ISCLEARED
$ATA !
%6
$ATA. .! 0
%6? %6
AI
%6?
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