ST STM32F105 series User Manual

DocID13902 Rev 15 310/1128
RM0008 Advanced-control timers (TIM1&TIM8)
359
Figure 80. Output stage of capture/compare channel (channel 1 to 3)
Figure 81. Output stage of capture/compare channel (channel 4)
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
14.3.6 Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
Output mode
CNT>CCR1
CNT=CCR1
controller
TIM1_CCMR1
OC1M[2:0]
OC1REF
OC1CE
Dead-time
generator
OC1_DT
OC1N_DT
DTG[7:0]
TIM1_BDTR
‘0’
‘0’
CC1E
TIM1_CCER
CC1NE
0
1
CC1P
TIM1_CCER
0
1
CC1NP
TIM1_CCER
Output
enable
circuit
OC1
Output
enable
circuit
OC1N
CC1E
TIM1_CCER
CC1NE
OSSI
TIM1_BDTR
MOE OSSR
0x
10
11
11
01
x0
ETR
controller
To the master mode
Output mode
CNT > CCR4
CNT = CCR4
controller
TIM1_CCMR2
OC2M[2:0]
OC4 REF
0
1
CC4P
TIM1_CCER
Output
enable
circuit
OC4
CC4E
TIM1_CCER
OSSI
TIM1_BDTR
MOE
To the master mode
controller
TIM1_CR2
OIS4
ETR

ST STM32F105 series Specifications

General

Brand	ST
Model	STM32F105 series
Category	Microcontrollers
Language	English