Flexible static memory controller (FSMC) RM0008
523/1128 DocID13902 Rev 15
WAIT management in asynchronous accesses
If the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase) programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase (DATAST in FSMC_BTRx register) must be programmed so that the
WAIT signal meets the following conditions:
• For read accesses: WAIT can be detected 4 HCLK cycles before data is being sampled
or 6 HCLK cycles before NOE is deasserted (refer to Figure 199: Asynchronous wait
during a read access).
• For write accesses: WAIT can be detected 4 HCLK cycles before NWE deassertion
(refer to Figure 200: Asynchronous wait during a write access).
1 MUXEN 0x1
0 MBKEN 0x1
Table 124. FSMC_BTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x0
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN
Duration of the last phase of the access (BUSTURN+1 HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles for
read accesses and DATAST+1 HCLK cycles for write accesses).
This value cannot be 0 (minimum is 1)
7-4 ADDHLD
Duration of the middle phase of the access (ADDHLD+1 HCLK
cycles).This value cannot be 0 (minimum is 1).
3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles).
Table 123. FSMC_BCRx bit fields (continued)
Bit No. Bit name Value to set
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