ST STM32F105 series User Manual

DocID13902 Rev 15 412/1128
RM0008 General-purpose timers (TIM2 to TIM5)
417
15.4.11 TIMx prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15.4.12 TIMx auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000
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PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event.
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ARR[15:0]
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Bits 15:0 ARR[15:0]: Prescaler value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 15.3.1: Time-base unit on page 362 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
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CCR1[15:0]
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Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

ST STM32F105 series Specifications

General

Brand	ST
Model	STM32F105 series
Category	Microcontrollers
Language	English