DocID13902 Rev 15 512/1128
RM0008 Flexible static memory controller (FSMC)
555
The differences compared with mode1 are the toggling of NOE and the independent read
and write timings.
Table 111. FSMC_BCRx bit fields
Bit
number
Bit name Value to set
31-20 Reserved 0x000
19 CBURSTRW 0x0 (no effect on asynchronous mode)
18:16 Reserved 0x0
15 ASYNCWAIT
Set to 1 if the memory supports this feature. Otherwise keep at
0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect on asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 WRAPMOD 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN Don’t care
5-4 MWID As needed
3-2 MTYP As needed, exclude 0x2 (NOR Flash)
1 MUXEN 0x0
0 MBKEN 0x1
Table 112. FSMC_BTRx bit fields
Bit
number
Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x0
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles) for
read accesses.
This value cannot be 0 (minimum is 1).
7-4 ADDHLD Don’t care
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) for
read accesses.
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