Revision history RM0090
1724/1731 DocID018909 Rev 11
28-Jul-2015
10
(Continued)
General-purpose timers (TIM9 to TIM14)
– Added the note in Section 19.3.12: Timer synchronization
(TIM9/12),
– Added the note to MMS2 bit description,
– Added the note to SMS[2:0] bit description in Section 19.4.2:
TIM9/12 slave mode control register (TIMx_SMCR).
Window watchdog (WWDG)
– Updated.Figure 214: Watchdog block diagram
Controller area network (bxCAN)
– Replaced tCAN with tq,
Flexible static memory controller (FSMC)
– Added the paragraph about Cross boundary page for Cellular RAM
1.5 in Section 36.5.5: Synchronous transactions,
– Updated MEMHIZx, MEMHOLDx, MEMSETx bit field descriptions
for FSMC_PME2..4 register in Section 36.5.5: Synchronous
transactions,
– Updated ATTSET, ATTHOLD, ATTHIZ bit field descriptions for
FSMC_PATT2..4 register in Section 36.5.5: Synchronous
transactions,
– Updated IRS and IFS bit descriptions for FMC_SR2..4 in
Section 36.5.5: Synchronous transactions,
– Renamed ADDSET as ADDSET[3:0] and MTYP as MTYP[1:0],
– Addition of CPSIZE in FSMC_BCRx bit fields in Table 221:
FSMC_BCRx bit fields, Table 223: FSMC_BCRx bit fields,
Table 226: FSMC_BCRx bit fields, Table 229: FSMC_BCRx bit
fields, Table 232: FSMC_BCRx bit fields, Table 235: FSMC_BCRx
bit fields, Table 237: FSMC_BCRx bit fields,
– Added CPIZE[2:0] in FMC_BCR1...4 registers in ,Section 36.5.6:
NOR/PSRAM control registers Section NOR/PSRAM control re
– Added CPSIZE[2:0] for FMC_BCRx registers in Section 36.6.9:
FSMC register map.
Table 310. Document revision history (continued)
Date Version Changes
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