DocID018909 Rev 11 1725/1731
RM0090 Revision history
1726
28-Jul-2015
10
(Continued)
Flexible memory controller (FMC)
– Added the paragraph about Cross boundary page for Cellular RAM
1.5 in Section 37.5.5: Synchronous transactions,
– Updated BUSTURN bit field description for FMC_BTR1..4 register
in Section 37.5.6: NOR/PSRAM controller registers,
– Updated MEMHIZx, MEMHOLDx, MEMSETx bit field descriptions
for FMC_PME2..4 register in Section 37.6.8: NAND Flash/PC
Card controller registers,
– Updated ATTSET, ATTHOLD, ATTHIZ bit field descriptions for
FMC_PATT2..4 register in Section 37.6.8: NAND Flash/PC Card
controller registers,
– Updated IRS and IFS bit descriptions for FMC_SR2..4 in
Section 37.6.8: NAND Flash/PC Card controller registers,
– Updated the section SDRAM initialization with the last item in the
numbered list in Section 37.7.5: SDRAM controller registers,
– Renamed ADDSET as ADDSET[3:0] and MTYP as MTYP[1:0],
– Addition of CPSIZE in Table 264: FMC_BCRx bit fields, Table 266:
FMC_BCRx bit fields, Table 269: FMC_BCRx bit fields, Table 272:
FMC_BCRx bit fields, Table 275: FMC_BCRx bit fields, Table 278:
FMC_BCRx bit fields, Table 280: FMC_BCRx bit fields, Table 282:
FMC_BCRx bit fields,
– Added the paragraph about Cross boundary page for Cellular RAM
1.5 in Section 37.5.5: Synchronous transactions,
– Added CPIZE[2:0] in FMC_BCR1...4 registers in Section 37.5.6:
NOR/PSRAM controller registers,
– Added CPSIZE[2:0] for FMC_BCRx registers in Section 37.8: FMC
register map.
Table 310. Document revision history (continued)
Date Version Changes
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