XLi Time & Frequency System 185
XLi-man, Issue 8, 6/17/2008, Rev. H
2
5
1
SSSSSSSSSSSS SSSSSSSSSS SSSSSSS S SSS S SSSSS S
Output Signal Frequency Selection
* This is the factory setting. For Output 1, a factory-configured option, Composite Clock, is available.
Contact H: Sales and Customer Assistance (page 295)
for more information.
Installation
Disconnect power from the XLi. Remove a blank panel from the rear of the XLi chassis, by unscrewing
the two screws securing it. Insert the edges of the T1 card into the grooves of the guide rails in the empty
option slot. Firmly push the T1 card into the option slot so the connector on the back of the card engages
the backplane connector completely and the front of the card is flush with the adjacent surfaces on the
back of the XLi. Secure the T1 card using the previously removed screws.
Operation
No special operation procedures are required. However, configuration of the Major and Minor faults
using F73 affect the operation of this option when AIS and Output signal control is enabled via DIP
switch S1, position 8.
Note: Alarm Relay closures are silk-screened on the panel above the wire wrap pins. These silk-screen
legends indicate the non-energized state of the relay closures. During normal operation, the
relays are energized so that a power failure would indicate a fault condition. Therefore the Alarm
state is the non-energized state and is in agreement with the silk-screened legends.
Theory of Operation
The XLi provides accurate time and frequency whenever the clock is locked to a reference source.
However, the accuracy and stability of this card’s outputs are characteristic of the internal oscillator or
Aux Ref to which they are phase locked. When the XLi is equipped with an optional OCXO or Rubidium
oscillator, this card is capable of providing Telecommunications Stratum I, Primary Reference Source
performance.
Alarm Operation
The logic resident in the FPGA, U7 implements major and minor alarm generation by monitoring two
bytes broadcast once-per-second over the XLi bus by the host microprocessor, and the /LFA and /LFB
signals sourced by U8 and U9, which indicate T1 output line faults.
Output 1 Output 2 Output 3 Output 4
Jumper Block JP7 JP6 JP5 JP4
64 Kb/s Pos.6 Pos.6 Pos.6 Pos.6
8 Kb/s Pos.5 Pos.5 Pos.5 Pos.5
1544 Kb/s Pos.4 Pos.4* Pos.4* Pos.4*
1 Mb/s Pos.3 Pos.3 Pos.3 Pos.3
5 Mb/s Pos.2 Pos.2 Pos.2 Pos.2
10 Mb/s Pos.1 Pos.1 Pos.1 Pos.1
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