Symmetricom XLi - Clock Architecture

XLi Time & Frequency System 3
XLi-man, Issue 8, 6/17/2008, Rev. H
2
5
1
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Clock Architecture
The following figures provide a simplified view of the XLi’s clock architecture.
Figure 1: Functional Timing Block Diagram
Aux Ref - 1/5/10 MHz
Rate Generation
Code Generation
Clock Machine
Phase Compare
200 MHz PLL
10 MHz Osc.
DAC
DAC Select
Clock DPLL
Phase Measurement
16.384 MHz Osc. PLL
1 PPS Timing Select
Time and Clock
Recovery
Code Input
1 PPS Output
Code Output
Rate Output
Aux Ref
1 PPS A
1 PPS B
Code Input
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