AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
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PRU-ICSS/MII0 Signals Description (continued)
TYPE
SIGNAL NAME [1] DESCRIPTION [2] ZCE BALL [4] ZCZ BALL [4]
[3]
pr1_mii0_txd0 MII Transmit Data bit 0 O W17, W3 T2, V13
pr1_mii0_txd1 MII Transmit Data bit 1 O T13, W2 R12, T1
pr1_mii0_txd2 MII Transmit Data bit 2 O U13, V2 R4, T12
pr1_mii0_txd3 MII Transmit Data bit 3 O U12, V1 R3, U12
pr1_mii0_txen MII Transmit Enable O T12, U2 R2, T11
pr1_mii_mr0_clk MII Receive Clock I W6 V4
pr1_mii_mt0_clk MII Transmit Clock I U1, V15 R1, U10
PRU-ICSS/MII1 Signals Description
TYPE
SIGNAL NAME [1] DESCRIPTION [2] ZCE BALL [4] ZCZ BALL [4]
[3]
pr1_mii1_col MII Collision Detect I R15 T17
pr1_mii1_crs MII Carrier Sense I V16, W7 R6, V12
pr1_mii1_rxd0 MII Receive Data bit 0 I NA V16
pr1_mii1_rxd1 MII Receive Data bit 1 I NA T15
pr1_mii1_rxd2 MII Receive Data bit 2 I NA U15
pr1_mii1_rxd3 MII Receive Data bit 3 I NA V15
pr1_mii1_rxdv MII Receive Data Valid I NA T16
pr1_mii1_rxer MII Receive Data Error I NA V17
pr1_mii1_rxlink MII Receive Link I V18 U18
pr1_mii1_txd0 MII Transmit Data bit 0 O NA R14
pr1_mii1_txd1 MII Transmit Data bit 1 O NA T14
pr1_mii1_txd2 MII Transmit Data bit 2 O NA U14
pr1_mii1_txd3 MII Transmit Data bit 3 O NA V14
pr1_mii1_txen MII Transmit Enable O W18 U17
pr1_mii_mr1_clk MII Receive Clock I NA U16
pr1_mii_mt1_clk MII Transmit Clock I NA R13
PRU-ICSS/UART0 Signals Description
TYPE
SIGNAL NAME [1] DESCRIPTION [2] ZCE BALL [4] ZCZ BALL [4]
[3]
pr1_uart0_cts_n UART Clear to Send I A18, E17 A17, D18
pr1_uart0_rts_n UART Request to Send O B18, D19 B17, D17
pr1_uart0_rxd UART Receive Data I B17, D18 B16, D16
pr1_uart0_txd UART Transmit Data O A17, C19 A16, D15
66 Terminal Configuration and Functions Copyright © 2011–2015, Texas Instruments Incorporated
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