Xilinx Spartan-6 FPGA Series User Manual

Spartan-6 FPGA PCB Design and Pin Planning www.xilinx.com 59
UG393 (v1.1) April 29, 2010
Microstrip/Stripline Bends
For wide traces, curved routing can also be helpful as shown in Figure 5-20.
X-Ref Target - Figure 5-19
Figure 5-19: Simulated Phase Response of 45 Degree Bends with Jog-Outs
X-Ref Target - Figure 5-20
Figure 5-20: Measured TDR of 45 Degree Bends with and without Jog-Outs
-75
-76
-77
4.95
Frequency, GHz
5.00
Phase(S(4,2))
Phase(S(3,1)) Phase(S(8,6)) Phase(S(7,5))
UG393_c5_19_091809
UG393_c5_20_091809
No Jog-outs
No Jog-outs
With Jog-outs
With Jog-outs
Turns & Jog-outs
Turns
Skew
50 mV, 200 ps Per Div.
10 mV, 100 ps Per Div.

Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156